One or more aspects of the present invention relate in general to the field of a multiprocessor system with a hierarchical cache structure, and in particular to a data processing system comprising multiple processors with a hierarchical cache structure comprising multiple levels of cache between the processors and a main memory.
Known data processing systems comprising multiple processors with hierarchical processor caches and a main memory share at least one processor cache between the processors. In such data processing systems the bandwidth between memory and processors is the new bottleneck. To increase the payload the known data processing systems comprise page mover functionality for moving data blocks from one memory location to another memory location without involving the corresponding processor that has initiated the data moving process.
In the Patent Application Publication US 2011/0320730 A1 “NON-BLOCKING DATA MOVE DESIGN” by Blake et al., incorporated by reference herein in its entirety, a mechanism for data buffering is disclosed. A portion of a cache is allocated as buffer regions, and another portion of the cache is designated as random access memory. One of the buffer regions is assigned to a processor. A data block is stored from one of the buffer regions of the cache to the memory.